1. Field of the Invention
This invention relates to digital cameras, and more particularly to a digital camera which is adapted to convert an image signal outputted, for example, from a CCD imager into image data, and supply the image data to an output circuit through a memory such as a VRAM.
2. Description of the Invention
The conventional digital camera of this kind uses a memory for temporarily storing image data and a DRAM (Dynamic Random Access Memory) having, for example, 4M bytes having a function as a working memory for the CPU, wherein a VRAM (Video RAM) of, for example, 1M byte is provided separately from the VRAM in order to store the data to be displayed on a monitor.
In this manner, the conventional digital camera requires two memories and accordingly, there exist problems of not only difficulties in size reduction but also high cost.
Therefore, it is a primary object of this invention to provide a digital camera that is low in price.
It is another object of this invention to provide a digital camera that is reduced in price and size by decreasing the number of memories used therefor.
According to this invention, a digital camera adapted to convert a progressive scan signal as an image signal into an interlace scan signal, comprises: a signal output means for outputting a progressive scan signal; a memory means for storing the progressive scan signal; a bus for connecting between the signal output means and the memory means; a request output means for outputting a request signal that request a release of the bus; a CPU for responding to the request signal to output a grant signal that grants the release of the bus; a writing means for responding to the grant signal to write the progressive scan signal into the memory means; and a reading means for reading from the memory means and odd-numbered field related signal related to an odd-numbered field and an even-numbered field related signal related to an even-numbered field.
The CPU releases the bus in response to the request signal. The writing means writes the progressive scan signal according, for example, to DMA (Direct Memory Access) into the memory means through the bus. At this time, the memory means of the CPU is prohibited from being accessed. When the writing of the image signal into the memory means is ended, a request output means cancels the request signal. In response thereto, the CPU can access to the memory means through the bus. Therefore, the memory at this time is utilized as a working memory for the CPU. Since the memory means can be utilized not only as a VRAM for storing image signals but also a working memory for the CPU, it is possible to reduce the number of memories as compared to that of the conventional art. It is therefore possible to obtain an inexpensive and small-sized digital camera.
The memory means, preferably, includes a memory having a plurality of memory locations each having a plurality number of bits, an input port for inputting therein the progressive scan signal and an output port for outputting therefrom the odd-number field related signal and the even-numbered field related signal.
In one aspect of this invention, the writing means writes an odd-numbered line of the progressive scan signal into higher-order bits, and an even-numbered line of the progressive scan signal into the lower-order bits of the progressive scan signal. Also, the reading means simultaneously reads the image signals written in the higher-order bits and the lower-order bits of the reading means to obtain 1 line of the odd-numbered field related signal or even-numbered field related signal.
In one embodiment of this invention, a CCD imager has a color filter having a same color arrangement repeated on every 2 lines. The progressive scan signal is created based on the output of the CCD imager. An RGB signal creating means creates an RGB signal based on the 1 line of interlace scan signal.
In another aspect of this invention, the writing means writes the progressive scan signal at a first high-speed clock rate, that is more than twice a reference clock rate, into the memory means, and the reads means separately reading the odd-numbered field related signal and the even-numbered field related signal at a second high-speed clock rate, more than twice the reference clock rate, from the memory means. The odd-numbered field related signal and the even-numbered field related signal thus read correspond to an interlace scan signal. Since the progressive scan signal is written at the high-speed clock rate into the memory means and the odd-numbered field related signal and the even-numbered field related signal are separately read at the high-speed clock rate from the memory means, the memory means can use a single-port memory, thus reducing cost.
In a preferred embodiment of this invention, the writing means writes the progressive scan signal inputted at the reference clock rate into the frame memory through a first line memory having a capacity of 1 line. Meanwhile, the reading means reads 2 lines of the progressive scan signal at one time from the frame memory to obtain an odd-numbered field related signal or even-numbered field related signal. The odd-numbered field related signal and the even-numbered field related signal are outputted at the reference clock rate through the second line memory having a capacity of 2 lines.
Further, according to this invention, a digital camera, comprises: a CCD imager; an image data output means for outputting image data based on an image signal from the CCD imager; a memory having a plurality of memory locations each configured by a plurality of bits and an input port and an output port respectively connected to a writing bus and a reading bus; a CPU; a bus for connecting between an output of the image data output means, the writing bus and the CPU; a memory control means for outputting a bus release request to the CPU to write the image data from the image data output means through the bus to the memory; and an output circuit for processing the image data outputted from the reading bus.
The image signal from the CCD imager is supplied, for example, through a CDS/AGC to an A/D converter included in the image data output means where it is converted into image data. The image data is further subjected, for example, to digital-clamping, white-balance adjustment, and gamma-correction by the image data output means, and then outputted from the image data output means.
The memory control means provides a bus release request, e.g. BUSREQUEST, to the CPU. The CPU responds to this bus release request to end a process being executed, to send back a grant of using the first bus, e.g. BUSGRANT, to the memory control means and release the first bus. Consequently, at this time the image data from the image data output means is supplied, according to DMA (Direct Memory Access), to a writing bus for the memory through the first bus. At this time, the CPU memory is prohibited from being accessed.
When the writing of the image data into the memory is ended, the memory control means cancels the bus release request. In response thereto, the CPU becomes accessible to the memory through the first bus and writing bus. Therefore, at this time the memory is utilized as a working memory for the CPU.
According to this invention, the memory can be utilized not only, for example, as a VRAM for storing image data but also as a working memory for the CPU, thereby making it possible to reduce the number of memories as compared with the conventional art. It is therefore possible to obtain a digital camera that is inexpensive and has a reduced size.
The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.